There is currently a trend in the radio market toward trunking radio systems and digital radio systems. Such radio systems require higher switching speeds than traditional single loop frequency synthesizers can provide at the required frequency resolution. In addition, regulatory agencies are requiring tighter channel spacing and assigning splinter frequencies. This has increased the local oscillator frequency resolution requirements of both analog and digital transceivers. In traditional single loop frequency synthesizers, switching time and phase noise go up as frequency resolution requirements tighten. In addition high data rate digital radio systems require lower phase noise and faster switching time than current analog radio systems.
Alternate technology of using separate receiving and transmitting frequency synthesizers can solve the switching speed problem but with higher costs, higher power consumption and the possibility of interference from the other frequency synthesizer. In addition, this approach does not solve the phase noise or frequency resolution problems.
Thus, there has developed a technique called fractional-N frequency synthesis which enables the use of a frequency synthesizer providing high switching speeds and low phase noise.
The origins of frequency synthesizers utilizing fractional-N techniques are divide-by-N frequency synthesizers including an integer divider arranged in a feedback loop from a tunable oscillator to a phase comparator provided with a reference frequency. Such frequency synthesizers generate an output frequency having a frequency which is an exact multiple of the reference frequency (the multiple being the integer N set in the integer divider). More specifically, such frequency synthesizers utilize a phase lock loop (PLL) to provide a variable frequency output signal having a selectable, precise and stable frequency.
Typically, as shown in FIG. 1, such a frequency synthesizer includes a voltage controlled oscillator (VCO) 100, a phase detector 102 (also commonly referred to as a phase comparator) and an integer divider or divisor circuit 104 interposed between the VCO 100 and the phase detector 102. The output frequency fout of the VCO 100 is divided by a selectable divisor N in the integer divider 104 and then compared to a known reference frequency fref by means of the phase detector 102. The phase detector 102 generates an output signal that is proportional to the phase difference between the known reference frequency fref and the output frequency from the VCO 100 after being divided by the divisor N in the integer divider 104 (the frequency being input to the phase detector 102 thus being fout/N). The output of the phase detector 102 is coupled back to the input of the VCO 100 through a loop filter 106 to tune and lock the VCO 100 to a desired frequency. The output frequency fout of the VCO 100 will then be an exact multiple of the reference frequency (fout=N fref). With the integer divider 104, the divisor can only be an integer so that the smallest increment in the output frequency fout is necessarily equal to the reference frequency, fref, itself, that is, the output signal can only be fref, 2fref, 3fref, etc. and cannot be a frequency between fref and 2fref or between 2fref and 3fref, etc.
A drawback of such a frequency synthesizer is that in order to provide a frequency synthesizer having a small step size between adjacent output frequencies, a very low reference frequency is required. Further, it is a drawback that in order to maintain the stability of the loop, the bandwidth of the filter 106 should be set at one tenth or less of the reference frequency. This narrow bandwidth results in slow switching time when switching from one output frequency to another. Finally, the low reference frequency causes a large multiplication of the inherent noise in the loop components, thereby increasing the phase noise on the output frequency.
In an attempt to address these drawbacks and limitations, a technique we call analog fractional-N synthesis was developed to synthesize an output signal having a frequency which is a rational number multiple of the reference frequency. A typical analog fractional-N synthesizer is shown in FIG. 2.
While the term “fractional synthesis” suggests division by a fractional value, the actual division is fractional only in terms of an average value. That is, since the integer divider 104 is able to divide only by an integer, fractional division is simulated by changing the divisor value temporarily during the course of an operation. Thus, a non-integer division ratio is realized by dividing by N+1, for example, instead of N, on a proportional number of division cycles to provide an average division ratio which approximates the desired divisor. This procedure is sometimes referred to as pulse swallow or pulse removal. The sequence of pulses to control the temporary changes in the divisor value is generated by an accumulator 108.
The accumulator 108 is a readily available electrical component which is driven at a clock frequency and provides an overflow or carry signal when it is completely full. The overflow signal is used to modify the divisor of the integer divider 104, for example, to change the divisor from N to N+1. The timing of the generation of the overflow signal is based on the number of states of the accumulator (designated P) and a desired fractional value programmed in the accumulator (designated F). Thus, the average value of the overflow signal of the accumulator 108 will represent the fraction F/P and will cause the divisor in the integer divider 104 to change from N to N+1 at the necessary times to cause the average output frequency fout of the VCO 100 to be equal to (N+F/P)*fref.
While the average output frequency is correct, it was found that a large phase error is generated by the phase detector. This phase error is substantially equal to the contents of the accumulator. Thus, to remove this phase error, a clocked digital-to-analog converter (DAC) 110 is added to provide the accumulator contents to a summer 112, interposed between the phase detector 102 and the loop filter 106, which cancels the error.
A drawback of frequency synthesizers utilizing analog fractional-N synthesis is that the phase detector has a large sawtooth phase error and therefore very accurate cancellation of this error is required to meet the needs of communication transceivers. As a practical matter, this means the reference frequency must be maintained at a relatively low frequency for suitable error cancellation (for example, 100–300 kHz) and also, the linearity of the phase detector and DAC are critical for cancellation of this error. As such, a frequency synthesizer utilizing analog fractional-N synthesis while an improvement over a divide-by-N frequency synthesizer, has a moderately slow switching speed and moderately high phase noise due to the low reference frequency required for error cancellation.
In view of the drawbacks and limitations of analog fractional-N synthesizers, frequency synthesizers based on sigma-delta converters or modulators were developed. Sigma-delta conversion is a well known technology used widely in analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) in high performance products such as CD players.
FIG. 3 is a block diagram of a fractional-N frequency synthesizer utilizing a sigma-delta converter. The frequency synthesizer includes a sigma-delta converter 114 and an integer divider 104 which divides the output frequency of the VCO 100 by a signal based on a division control number N+F/P. The division control number is made up of an integer portion N and a fractional portion F/P. The sigma-delta converter 114 receives the fractional value F, and a clock signal which is derived from the reference frequency fref or the output frequency fout. The sigma-delta converter 114 provides a series of integer value corrections as output which represents on average the fractional portion F/P. The integer value corrections are summed with the integer portion N in a summer 116 to obtain the division control number (N+F/P).
FIG. 4 is a block diagram of a specific implementation of a sigma-delta converter often referred to as a MASH 111. The manner in which the converter functions to provide the fractional output F/P with P being the number of states in the accumulator is understood by those skilled in the art. For example, reference is made to U.S. Pat. Nos. 4,694,475, 4,758,802, 4,800,342, 4,996,699, 5,038,117 and 5,055,802 among others.
One of the properties of sigma-delta converters is that the phase error is never totally eliminated, but rather, it is changed from discrete spurious signals to noise and this noise is reduced at low frequencies by noise shaping.
In this regard, if noise from sigma-delta converter were flat, the spectral density would be proportional to 1/fref. This would require a very high clock frequency in the sigma-delta converter to reduce the noise adequately for synthesizer applications. Instead, Sigma-Delta Converters are designed to shape the phase noise. For instance a MASH111 converter used in a fractional N synthesizer has an output phase noise spectrum of:δ2(2π)2/(12fref)(1−z−1)2(m−1) rad2/Hzwhere m is the order of the sigma-delta converter, and δ is the quantizer step size. This step is equal to one for traditional sigma-delta fractional-N synthesis. For high sample rates (compared to loop bandwidth) and δ=1, for a third order sigma-delta converter, the noise can be approximated as:(2π)2/(12fref) (2πf/fref)4 rad2/Hz(See, for example, Brian Miller, A Multiple Modulator Fractional Divider”. IEEE Transactions on Instrumentation and Measurement, vol. 40, No. 3, June 1991, pp. 578–583). Thus, if the order and bandwidth of the PLL are selected correctly, the noise from the Sigma-Delta Converter will be low inside of the loop bandwidth and the PLL will filter off the Sigma-Delta noise at higher frequencies.
There are practical limitations on the fractional-N frequency synthesizer shown in FIG. 3. For example, a higher phase detector linearity is required than in frequency synthesizers using analog fractional-N techniques since, for instance, a MASH111 sigma-delta converter changes N by eight counts (from −3 to +4) instead of two counts (0 and 1) in the analog fractional-N technique. Thus, the performance of the frequency synthesizer shown in FIG. 3 can be limited by phase detector linearity.
Another drawback of the use of the sigma-delta converter shown in FIG. 4 is that the calculations in the accumulators and the differentiators are performed at the reference frequency. In view of the relatively large number of bits involved in the computation of the integer for the integer divider 104, a large number of computations must be performed resulting in relatively large power requirements.
There have been numerous attempts to improve the performance of fractional-N frequency synthesizers by reducing spurious signals and noise. Of particular interest, U.S. Pat. No. 4,965,531 (Riley) describes a frequency synthesizer including a fractional-N divider having two sigma-delta converters connected in cascade by means of a summer. The output control signal of one sigma-delta converter is applied to the input of the summer which combines the output control signal with another control signal. The combined control signal is applied to the other sigma-delta converter. The output control signal of this sigma-delta converter is said to be capable of displacing quantization noise in the signal away from frequencies of the phase control signal being directed to the phase detector as well as multiple thereof.
A significant drawback of the frequency synthesizer of Riley is that both sigma-delta converters are driven at the same clock frequency, i.e., the output frequency from the integer divider. As such, Riley does not achieve any reductions in costs or computational load resulting from the use of cascading sigma-delta converters since both sigma-delta converters are driven at the same relatively high clock frequency.
It would thus be advantageous to provide a fractional-N frequency synthesizer which offers the same elimination of noise and spurious signals, and has a reduced cost in comparison with prior art frequency synthesizers, because it requires fewer computations than prior art frequency synthesizers.